The invention is directed to a CMOS-RAM memory in a gate array arrangement composed of seven transistor basic cells wherein a memory cell can be realized with a basic cell.
Gate array arrangements are known (for example, Hitachi Review, Vol. 33 (1984) No. 5, Pages 261-266). In such gate array arrangements, regions are provided on a chip in a specific arrangement in which basic cells are realized. The basic cells are composed of n-channel and p-channel transistors that are arranged in the regions in a specific way. A basic cell can be tailored for realizing a basic function by connecting the n-channel and p-channel transistors per basic cell and, for example, it can be given a logical function or a storing function. It derives from Hitachi Review that was cited above that a basic cell can be composed of, for example, ten transistors that are connected such to one another such that a RAM memory cell having an input or two inputs arises. For example, a logic function, for example, a NAND function, can be realized by other connections of the transistors in a basic cell.
The realization of memories having different capacities was heretofore achieved in various ways. Bistable circuits were employed for low-capacity storing structures. These were composed of a plurality of gates and therefore require a relatively great number of basic cells of a gate array for storing an informational unit. High-capacity memories were realized in that a memory block having a defined capacity and designed as a general cell was integrated in the core region of the chip. As a result the capacity of a memory can only be selected in steps of the memory capacity of this general cell. The area reserved for the general cells can thus only be used for the memory, and not for other logical functions.